In a typical wireless communications system, timing must be synchronized between a digital wireless communications terminal and a base station. A high accuracy crystal clock source is generally used in the terminal to maintain a timebase (i.e., a timing reference for operating the terminal). In some modes of operation, such as a paging mode when the communications terminal is waiting for incoming calls, the communications terminal ordinarily does not have to perform any tasks for periods of up to several seconds. However, even if the terminal is designed to enter a power saving mode after not receiving an incoming call for a certain period of time, the communications terminal must still be able to receive appropriate timeslot and other service information during the idle time. Therefore, the timebase must still be maintained even while in these standby or power saving modes.
For current complementary metal oxide semiconductor (CMOS) integrated circuits used in communications terminals, power consumption is directly related to clock frequency. As is known to those skilled in the art, the higher frequency, higher accuracy crystals consume more power. Consequently, the high frequency crystal clock sources and the circuits connected to these clock sources dissipate a significant amount of power even during these standby paging modes.
Commnunications terminals used in the Global System for Mobile Communications (GSM), which is a Pan-European standard for digital cellular phone service, are an example of a device that would benefit from the implementation of an effective power saving scheme. In a GSM system, the timebase is generally provided by a 13 MHz crystal clock source. Although the 13 MHz clock provides a highly stable timebase, the excessive power consumption during the paging mode adversely affects the overall system performance by reducing the battery life of the terminals. Generally, most types of communications systems, such as GSM, employ digital signal processors (DSPs) for the real-time processing of signals. These DSP-based systems are particularly demanding of clock and power resources due to the requirements associated with baseband data processing. Consumer audio applications, such as digital answering machines and digital cordless phones, could also benefit from an effective power saving scheme.
Some attempts have been made in the prior art to provide high accuracy clock circuits with a low power mode. One approach is to operate a low frequency, low power clock on a continuous basis as the primary timing source, and to periodically turn on a high frequency, high accuracy clock to tune the less stable clock. However, the low frequency clock, even with periodic tuning, cannot provide a timebase with the level of accuracy required in time division multiple access (TDMA) type systems such as GSM. The additional circuitry for tuning the low power clock also adds unnecessary design and fabrication constraints on the terminal.
Accordingly, there is still a critical need in the art for a power saving clock scheme that provides a low power mode of operation while maintaining a highly accurate timebase.